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Journal Publications:

  1. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner and Charlie Chungping Chen, " Correlation-Preserved Statistical Timing with Quadratic Form of Gaussian Variables ," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), 2005, to appear
  2. Lizheng Zhang, Weijen Chen, Yuhen Hu and Charlie Chungping Chen, " Statistical Static Timing Analysis with Conditional Linear MAX/MIN Approximation and Extended Canonical Timing Model," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), 2005, to appear
  3. Rong Jiang, Wenyin Fu and Charlie Chung-Ping Chen, " EPEEC: Comprehensive SPICE-Compatible Reluctance Extraction for High-Speed Interconnects above Lossy Multilayer Substrate," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), 2005, to appear
  4. Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, " Yield-Driven False-Path-Aware Clock-Skew Scheduling," IEEE Design & Test of Computers (D&T), Vol. 22, No. 3, pp. 214-222, May-June, 2005.
  5. Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, "HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 24, No. 6, pp. 797-806, June, 2005.
  6. Jeng-Laing Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen, "Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 23, No. 4, pp. 565-572, April, 2004.
  7. Charlie Chung-Ping Chen (陳中平教授), "SoC設計探勘突破SoC電氣設計的挑戰與解決方針," Micro-Electronics Magazine (新電子科技雜誌), Sep. 2003.
  8. Yu-Min Lee and Charlie Chung-Ping Chen, "The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 22, No. 11, pp. 1545-1550, Nov. 2003.
  9. Ting-Yuan Wang and Charlie Chung-Ping Chen, "Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method," IEEE Transaction on Very Large Scale Integration Systems (TVLSI), Vol. 11, No. 4, pp. 691-700, Aug. 2003.
  10. Tsung-Hao Chen, Clement Luk, and Charlie Chung-Ping Chen, "INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 22, No. 7, pp. 884-894, July 2003.
  11. Ting-Yuan Wang and Charlie Chung-Ping Chen, "3-D Thermal-ADI: a linear-time chip level transient thermal simulator," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 21, No. 12 , pp. 1434 -1445, Dec. 2002.
  12. Yu-Min Lee and Charlie Chung-Ping Chen, "Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 21, No. 11, pp. 1343 -1352, Nov. 2002.
  13. Yu-Min Lee, Charlie Chung-Ping Chen, and D. F. Wong, "Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes," IEEE Transactions on Circuits & Systems-I (TCAS-I) Vol. 49, No. 11, pp. 1671-1677, Nov. 2002.
  14. Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong, "Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 18, No. 7, pp. 1014-1025, July 1999.

Conference/Workshop Publications:

  1. Lizheng Zhang, Jun Shao and Charlie Chung-Ping Chen," Non-Gaussian Statistical Parameter Modeling for SSTA with Confidence Interval Analysis," ISPD, 2006, accepted.
  2. Lizheng Zhang, Yuhen Hu and Charlie Chung-Ping Chen," Statistical Timing Analysis with Path Reconvergence and Spatial Correlations," DATE, 2006, accepted.
  3. Sanghamitra Roy and Charlie Chung-Ping Chen," ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems," ISQED, 2006, accepted.
  4. Rong Jiang, Wenyin Fu, Janet Meiling Wang and Charlie Chung-Ping Chen," Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis," ICCAD, 2005.
  5. Sanghamitra Roy, Weijen Chen and Charlie Chung-Ping Chen," ConvexFit: An Optimal Minimum-Error Convex Fitting and Smoothing Algorithm with Application to Gate-Sizing ," ICCAD, 2005.
  6. Jeng-Liang Tsai, Lizheng Zhang and Charlie Chung-Ping Chen," Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis ," ICCAD, 2005.
  7. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner and Charlie Chung-Ping Chen," Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model ," DAC, 2005.
  8. Rong Jiang and Charlie Chung-Ping Chen," ICCAP: A Linear Time Sparse Transformation and Reordering Algorithm for 3D BEM Capacitance Extraction," DAC, 2005.
  9. Vikas Sharma, Chien-Liang Chen and Charlie Chung-Ping Chen," 1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer," GLSVLSI, 2005.
  10. Qi-Wei Kuo, Vikas Sharma and Charlie Chung-Ping Chen," Substrate-Bias Optimized 0.18um 2.5 GHz 32-bit adder with Post-Manufacture Tunable Clock," VLSI-TSA-DAT, 2005.
  11. Lizheng Zhang, Weijen Chen, Yu-Hen Hu and Charlie Chung-Ping Chen," Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model," DATE, 2005.
  12. Rong Jiang and Charlie Chung-Ping Chen," A Linear Time Implicit Congruence Sparsification Technique for BEM Capacitance Extraction," IMS, 2005.
  13. Hsinwei Chou, Yu-Hao Wang and Charlie Chung-Ping Chen," Fast and Effective Gate-Sizing with Multiple-Vt Assignment using Generalized Lagrangian Relaxation," ASPDAC, 2005.
  14. Rong Jiang and Charlie Chung-Ping Chen," Comprehensive Frequency Dependent Interconnect Extraction and Evaluction Methodology," ASPDAC, 2005.
  15. Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen," Wave-Pipelined On-Chip Global Interconnect," ASPDAC, 2005.
  16. Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen," Block-Based Statistical Timing Analysis with Extended Canonical Timing Model," ASPDAC, 2005.
  17. Jeng-Liang Tsai and Charlie Chung-Ping Chen, "Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling," ASPDAC, 2005.
  18. Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, "False Path and Clock Scheduling Based Yield-Aware Gate Sizing," VLSI Design, 2005.
  19. Tsung-Hao Chen, Jeng-Liang Tsai, Charlie Chung-Ping Chen and Tanay Karnik, "HiSIM: Hierarchical Interconnect-Centric Circuit Simulator," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004.
  20. Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, "A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004.
  21. Hsinwei Chou, Yu-Hao Wang and Charlie Chung-Ping Chen, " LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment," The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2004.
  22. Hsinwei Chou and Charlie Chung-Ping Chen, " A ROBDD-Based Generalized Nodal Control Scheme for Standby Leakage Power Reduction ," The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2004.
  23. Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, " Statistical Timing Analysis with AMECT: Asymptotic MAX/MIN Approximation and Extended Canonical Timing Model," The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2004.
  24. Rong Jiang and Charlie Chung-Ping Chen, " EPEEC: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Currents," IEEE Custom Integrated Circuits Conference (CICC), 2004.
  25. Lizheng Zhang, Yu Hen Hu, and Charlie Chung-Ping Chen, "Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining," IEEE/ACM Design Automation Conference (DAC), 2004.
  26. Rong Jiang and Charlie Chung-Ping Chen, "ESPRIT: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Current,"  International Microwave Symposium (IMS), 2004.
  27. Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, "Power-Delivery Networks Optimization with Thermal Reliability Integrity," ACM International Symposium on Physical Design (ISPD), 2004.
  28. Ting-Yuan Wang and Charlie Chung-Ping Chen, "SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis based on Model Reduction," 5th International Symposium on Quality Electronic Design (ISQED), 2004.
  29. Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, "Thermal and Power Integrity based Power/Ground Networks Optimization," Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004.
  30. Rong Jiang and Charlie Chung-Ping Chen, "SCORE: SPICE Compatible Reluctance Extraction," Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004.
  31. Rong Jiang and Charlie Chung-Ping Chen, "Realizable Reduction for Electromagnetically Coupled RLMC Interconnects," Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004.
  32. Lizheng Zhang, Yuhen Hu, and Charlie Chung-Ping Chen, "Wave-pipelined On-Chip Global Interconnect," ACM/IEEE TAU Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2004.
  33. Tsung-Hao Chen, Clement Luk, and Charlie Chung-Ping Chen, "SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2003.
  34. Rong Jiang, Tsung-Hao Chen, and Charlie Chung-Ping Chen, "PODEA: POwer Delivery Efficient Analysis with Realizable Model Reduction," IEEE International Symposium on Circuits and Systems (ISCAS), 2003.
  35. Ting-Yuan Wang, Yu-Min Lee, and Charlie Chung-Ping Chen, "3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator," ACM International Symposium on Physical Design (ISPD), 2003. ( Best Paper Award )

  36. Jeng-Laing Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen, "Epsilon-Optimal Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time," ACM International Symposium on Physical Design (ISPD), 2003.

  37. Yu-Min Lee and Charlie Chung-Ping Chen, "The Power Grid Transient Simulation in Linear Time based on 3D Alternating-Direction-Implicit Method," Design, Automation and Test in Europe Conference and Exhibition (DATE), 2003.
  38. Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, and Charlie Chung-Ping Chen, "INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor," IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2002.
  39. Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, and Charlie Chung-Ping Chen, "HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery," IEEE/ACM Design Automation Conference (DAC), 2002.
  40. Ting-Yuan Wang and Charlie Chung-Ping Chen, "Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm," Third International Symposium on Quality Electronic Design (ISQED), 2002.
  41. Yu-Min Lee and Charlie Chung-Ping Chen, "Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method," IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2001
  42. Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee and Charlie Chung-Ping Chen, "Linear Time Hierarchical Capacitance Extraction Without Multipole Expansion," International Conference on Computer Design (ICCD), 2001.
  43. Pradeepsunder Ganesh and Charlie Chung-Ping Chen, "RC-in RC-out Model Order Reduction Accurate Up to Second Order Moments," International Conference on Computer Design (ICCD), 2001.
  44. Tsung-Hao Chen and Charlie Chung-Ping Chen, "Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods," IEEE/ACM Design Automation Conference (DAC), 2001.
  45. Ting-Yuan Wang and Charlie Chung-Ping Chen, "Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method," ACM International Symposium on Physical Design (ISPD), 2001.  [slide]
  46. Yu-Min Lee, Hing Yin Lai, and Charlie Chung-Ping Chen, "Optimal spacing and capacitance padding for general clock structures," Asia and South Pacific Design Automation Conference (ASP-DAC), 2001.
  47. Yu-min Lee and Charlie Chung-Ping Chen, "Hierarchical model order reduction for signal-integrity driven interconnect synthesis," Great Lakes Symposium on VLSI (GLSVLSI), 2001.
  48. Charlie Chung-Ping Chen, Narayanan Murugesan, Tae-Woo Lee, and Susan C. Hagness, "FDTD-ADI: An Unconditionally Stable Full Wave Maxwell Equation Solver for VLSI Modeling," IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2000.
  49. Chung-Ping Chen and N. Menezes, "Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching," IEEE/ACM Design Automation Conference (DAC), 1999.
  50. Chung-Ping Chen and D.F. Wong, "Error-bounded Pade Approximation via Bilinear Conformal Transformation," IEEE/ACM Design Automation Conference (DAC), 1999.
  51. N. Menezes and Chung-Ping Chen "Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect," Twelfth International Conference on VLSI Design, 1999. 
  52. Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong, "Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1998.
  53. Chung-Ping Chen and D. F. Wong, "Optimal Wire-Sizing Function with Fringing Capacitance Consideration," IEEE/ACM Design Automation Conference (DAC), 1997.
  54. Chung-Ping Chen, Hai Zhou, and D. F. Wong, "Optimal Non-Uniform Wire-Sizing under the Elmore Delay Model," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1996.
  55. Chung-Ping Chen, Yao-Ping Chen, and D. F. Wong, "Optimal Wire-Sizing Formula under the Elmore Delay Model," IEEE/ACM Design Automation Conference (DAC), 1996.
  56. Chung-Ping Chen, Yao-Wen Chang, and D. F. Wong, "Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation," IEEE/ACM Design Automation Conference (DAC), 1996.
  57. Chung-Ping Chen and D. F. Wong, "A Fast Algorithms for Optimal Wire-Sizing under the Elmore Delay Model," IEEE International Symposium on Circuits and Systems (ISCAS), 1996.

Reports and Theses:

  1. Lizheng Zhang, "Statistical timing analysis for digital circuit design," PhD Thesis, 2005.
  2. Jeng-Liang Tsai, "Clock Tree Synthesis for Timing Convergence and Timing Yield Improvement in Nanometer Technologies," PhD Thesis, 2005.
  3. Hsinwei Chou, "Simultaneous delay, yield and total power optimization in deep-submicron CMOS technology using gate-sizing, threshold voltage assignment, nodal control, and technology mapping," MS Thesis, 2004.
  4. Clement Luk and Charlie Chung-Ping Chen, "Efficient Inductance Extraction for On-chip Interconnects," 2003.
  5. Tsung-Hao Chen, Hyoung-Suk Kim, and Charlie Chung-Ping Chen, "L Extracted? Now What? Introduction to An Inductance-Wise Interconnect Simulation Engine (INDUCTWISE)", Technical Report, University of Wisconsin-Madison, 2002.
  6. Hyungsuk Kim and Charlie Chung-Ping Chen, "Be Careful of Self and Mutual Inductance Formulae," 2001.

 

Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.

 

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