®2003
Ting-Yuan Wang

QuickTune

Yu-Hao Wang, Yu-Min Lee, and Charlie Chung-Ping Chen

Introduction

This utility program allows fast gate sizing for general VLSI circuits under the Elmore delay model. It uses a fast and exact algorithm that can minimize the maximum delay subject to arrival time specifications at all inputs and outputs. The algorithm is based on Lagrangian Relaxation, and the convergence to global optimal solutions is guaranteed.

Usage and data format

Command to execute the program under Unix or Windows

SGWS_LR [input filename][output filename][inner criteria][outer criteria]

ü  input filename: Circuit netlist file in ISCAS Benchmark format

ü  output filename: Output file containing both the circuit statistics and optimum gate-sizing solutions

ü  inner loop stopping criteria: The default stopping criteria is when the solution is within 0.0005% of an optimal Lagrange multiplier if unspecified [1]

ü  outer loop stopping criteria: The default stopping criteria is when the solution is within 1% of the optimal solution if unspecified [1]

Instances

Executable utility 

Gate Sizing by Lagrange Relaxation for Windows:  SGWS_LR.zip (143K); Solaris:  SGWS_LR.tar (893K). Source code: qt_src.zip.

Reference paper

[1] C. P. Chen, C. Chu, D. F. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1998. 

All questions and suggestions email to chen@engr.wisc.edu, yu-haow@cae.wisc.edu.

Last Updated: 2/6/2002

®2003 Ting-Yuan Wang   [ Home ] [ News ] [ Members ] [ Publications ] [ Tools ] [ Useful Links ] [ Presentations ] [ Projects ] [ Cadence ] [ SRC Project ] [ Forum ]