Introduction:
   The magnitude of the difficulties associated with the plunge of circuit designs into deep submicron process geometries has been the source of much speculation. In particular, the significant rise in the portion of critical path delay attributed to interconnect induces serious concerns while performing accurate analysis of interconnects. In addition, due to the rapidly increasing complexity and power consumption on a chip, the robustness of power delivery network is also another challenge during VLSI design. A powerful circuit simulation tool is usually required to deal with these problems. However, the huge number of transistors on a chip causes timing analysis tools facing a fact that it has to solve enormous sparse matrices. General-purpose simulator such as SPICE can almost not finish analyzing a circuit with millions nodes. 
    This tool is built to efficiently handle large-scale linear circuit with RLKC elements, which is able to simulate large signal integrity problems on huge interconnections. The result shows this tool, INDUCTWISE, is at least 20x faster than Tanner™ SPICE, which is known already much faster than SPICE3 (at least another 20x).
    Beside the traditional MNA solution, INDUCTWISE is capable to simulate the novel technology, K-elements (Sparsified inverse inductance matrix), which recently exposed great potential to capture the inductance effect on-chip. In addition, INDUCTWISE also integrates our Improved Extended Krylov Subspace (IEKS) method and a moment computation function into the same software. 

Product Feature: 

	Excellent Sparse Matrix Solver
	Capable to Simulate K-Element
	Improved Extended Krylov Subspace Method
	Function for Moment Calculation
	SPICE Language Compatible