![Home](_derived/home_cmp_vlsi-eda010_vbtn.gif)
![News](_derived/News.htm_cmp_vlsi-eda010_vbtn.gif)
![Members](_derived/Members.htm_cmp_vlsi-eda010_vbtn.gif)
![Publications](_derived/Publications.htm_cmp_vlsi-eda010_vbtn.gif)
![Tools](_derived/Tools.htm_cmp_vlsi-eda010_vbtn.gif)
![Useful Links](_derived/Links.htm_cmp_vlsi-eda010_vbtn.gif)
![Presentations](_derived/Presentations.htm_cmp_vlsi-eda010_vbtn.gif)
![Projects](_derived/Projects.htm_cmp_vlsi-eda010_vbtn.gif)
![Cadence](_derived/cadence.htm_cmp_vlsi-eda010_vbtn.gif)
![SRC Project](_derived/SRC.html_cmp_vlsi-eda010_vbtn.gif)
®2003
Ting-Yuan Wang
| |
INDUCTWISE
- Inductance-Wise
Interconnect Simulation Engine
(
New Version of our WPCG2.00 )
Tsung-Hao
Chen and
Charlie Chung-Ping
Chen
![bullet](_themes/vlsi-eda/amodbul1.gif) |
Introduction:
The magnitude
of the difficulties associated with the plunge of circuit designs into deep
submicron process geometries has been the source of much speculation. In
particular, the significant rise in the portion of critical path delay
attributed to interconnect induces serious concerns while performing
accurate analysis of interconnects.
In addition, due to the rapidly increasing complexity and power consumption
on a chip, the robustness of power delivery network is also another
challenge during VLSI design. A powerful circuit simulation tool is usually
required to deal with these problems. However, the huge number of
transistors on a chip causes timing analysis tools facing a fact that it has
to solve enormous sparse matrices. General-purpose simulator such as SPICE
can almost not finish analyzing a circuit with millions nodes.
This tool is built to efficiently handle large-scale
linear circuit with RLKC elements, which is able to simulate large signal integrity
problems on huge interconnections. The result shows this tool, INDUCTWISE,
is at least 20x faster than Tanner™ SPICE, which is known already much
faster than SPICE3 (at least another 20x).
Beside
the traditional MNA solution, INDUCTWISE
is capable to simulate the novel technology, K-elements (Sparsified
inverse inductance matrix), which recently exposed great potential to
capture the inductance effect on-chip. In addition, INDUCTWISE also
integrates our Improved Extended Krylov Subspace (IEKS) method and a moment
computation function into the same software.
|
![bullet](_themes/vlsi-eda/amodbul1.gif) |
Product Feature:
![bullet](_themes/vlsi-eda/amodbul2.gif) |
Excellent
Sparse Matrix Solver |
![bullet](_themes/vlsi-eda/amodbul2.gif) |
Capable
to Simulate K-Element |
![bullet](_themes/vlsi-eda/amodbul2.gif) |
Improved
Extended Krylov Subspace Method |
![bullet](_themes/vlsi-eda/amodbul2.gif) |
Function
for Moment Calculation |
![bullet](_themes/vlsi-eda/amodbul2.gif) |
SPICE
Language Compatible
|
|
![bullet](_themes/vlsi-eda/amodbul1.gif) | OS Requirement:
PC (Windows based) or SUN
|
![bullet](_themes/vlsi-eda/amodbul1.gif) | User's Guide for INDUCTANCE 1.00
|
![bullet](_themes/vlsi-eda/amodbul1.gif) | Download and Try It now!!
|
![bullet](_themes/vlsi-eda/amodbul1.gif) | Reference:
|
![bullet](_themes/vlsi-eda/amodbul1.gif) | License Infomation:
This program will expire after Aug 31, 2002. If you are
interested and want to know more about it, please contact the supervisor Professor
Charlie Chen (chen@engr.wisc.edu).
|
![bullet](_themes/vlsi-eda/amodbul1.gif) | Technical Support:
If you have any technical problem, please email the author Tsung-Hao Chen
(tchen@cae.wisc.edu)
of this tool. Please also report any bug you find to the author. Thanks very
much. |
|